-- 
-- author:   Claudio Talarico
-- file:     mux-tb-a.vhd
-- comments: silly tb for 2:1 mux
--

architecture beh of mux_tb is

  -- signal and variable declaration
  signal a : std_logic;
  signal b : std_logic;
  signal s : std_logic;
  signal z : std_logic;

  component mux
    port ( a : in  std_logic;
           b : in  std_logic;
           s : in  std_logic;
           z : out std_logic);
  end component mux;

begin
 
  mux_instance: mux
  port map (
    a => a,
    b => b,
    s => s,
    z => z );
  
  tb: process
  begin

    a <= '0';
    b <= '0';
    s <= '0';
    wait for 10 ns;
 
    a <= '0';
    b <= '0';
    s <= '1';
    wait for 10 ns;

    a <= '0';
    b <= '1';
    s <= '0';
    wait for 10 ns;

    a <= '0';
    b <= '1';
    s <= '1';
    wait for 10 ns;

    -- necessary for the simulator to advance
    wait for 10 ns;
    
    assert false
    report "End of TestBench"
    severity error;

  end process tb;
    
end architecture beh;