library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb_edge_detector is
  --empty
end tb_edge_detector;


architecture beh of tb_edge_detector is

  component edge_detector
        port(
                din   :  in  std_logic;
                clk   :  in  std_logic;
                rst_n :  in  std_logic;
                dout  :  out std_logic
            );
  end component edge_detector;


  --signal declaration

     signal clk        : std_logic;
     signal rst_n      : std_logic;
     signal din        : std_logic;
     signal dout       : std_logic;

 begin
        inst_1: edge_detector
          port map(
                  din   =>  din,
                  clk   =>  clk,
                  rst_n =>  rst_n,
                  dout  =>  dout
                  );

 
    clk_p : process
    begin
      clk <= '0';
      wait for 2 ns;
      clk <= '1';
      wait for 2 ns;
    end process clk_p;

    input_data : process
        begin
            din <= '0';
                wait for 7 ns;
            din <= '1';
                wait for 10 ns;
            din <= '0';
                wait for 20 ns;
        end process input_data;

    test_bench : process
        begin

          rst_n <= '0';
          wait for 1 ns;
          rst_n <= '1';
          wait for 100 ns;

          assert false
          report "End of Simulation"
          severity failure;

        end process test_bench;

end beh;