The main CAD tools we will be using is Xilinx ISE (Integrated Software Environment) WebPack.
ISE WebPack is a complete front-to-back end FPGA design solution and can be downloaded for free. Extensive information about Xilinx and its products can be found at:
For compiling and simulating your VHDL designs it is also possible to download and use the free
version of VHDL Simili 3.1 from Symphony EDA.
To get up to speed with the use of VHDL Simili try the following tutorial: